TW-G-03: Taiwan's Semiconductor Diaspora, TSMC's Global Fab Architecture, and Chip Diplomacy — From the Phoenix Fab-21 Phase 1 N4 Production Start to the Dresden ESMC Ground-Breaking, the Kumamoto JASM Sony-Joint-Venture Build, and the Lai-Government Chip-Diplomacy Doctrine (2020–2026)

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1. Key Takeaways

The post-2020 TSMC global-fab architecture — Arizona (Fab-21 Phase 1 N4 production start November 2024; Phase 2 N3 targeting 2028; Phase 3 N2 announced March 2025 targeting 2030), Kumamoto (JASM Fab 1 opened February 2024 at 12–28nm; JASM Fab 2 targeting 2027 at 6–7nm), and Dresden (ESMC ground-breaking 20 September 2024 at 12–28nm targeting 2027/2028) — constitutes the most-substantial geographic-diversification of leading-edge semiconductor manufacturing capacity since the 1990s East Asian foundry consolidation, and the structural reorganisation of the global semiconductor architecture that the Lai Ching-te (賴清德) administration's "silicon-shield 2.0" framing characterises as cross-Strait-strategic deterrence-thickening. The cumulative capital-expenditure commitment across the three sites — approximately USD 165 billion across the Arizona Phase 1–3 architecture (post-3 March 2025 USD 100 billion Oval-Office pledge), approximately JPY 2.9 trillion (approximately USD 19 billion) across the Kumamoto JASM Fab 1–Fab 2 architecture [TBD-VERIFY: precise cumulative JASM commitment varies across reporting; the JPY 2.9 trillion figure aggregates the Fab 1 JPY 1.1 trillion and Fab 2 JPY 1.8 trillion announcements], and approximately EUR 10 billion across the Dresden ESMC architecture [TBD-VERIFY: precise Dresden ESMC capex figure varies] — produces a total announced commitment of roughly USD 195 billion, the largest single-firm international capital-expenditure programme in semiconductor-industry history.
TSMC Arizona Fab-21 Phase 1 commenced N4 (4-nanometre) mass production in November 2024 — approximately one year behind the original 2024 target — with Apple as the lead announced customer and yield parity to the Tainan Fab 18 baseline reported by Q1 2025; Phase 2 (N3 / 3-nanometre) is targeting 2028 production, and the post-3 March 2025 Trump-Wei Oval-Office Phase 3 (N2 / 2-nanometre) announcement targets 2030 production. The Fab-21 Phase 1 ramp was marked by substantial labour-culture disputes, ASML EUV (extreme ultraviolet) equipment-install delays, construction-cost inflation, and the friction between TSMC-Taiwan management practices (long hours, 24/7 on-call expectations, military-discipline fab-floor norms) and US-Arizona workforce expectations including the Arizona Pipe Trades Local 469 and Sheet Metal Workers Local 359. The November 2024 N4 production-start — first announced commercial-volume Apple A-series chip [TBD-VERIFY: the December 2024 / January 2025 reporting variously cited A16-series and A18-series part numbers; TSMC's public language did not disclose precise part-number] — concluded the Phase 1 build-out and inaugurated the post-2024 commercial-production phase. The 3 March 2025 Oval-Office announcement by Chairman C.C. Wei (魏哲家) of an additional USD 100 billion commitment across three additional fabs, two advanced-packaging facilities, and an R&D centre raised the cumulative pre-March 2025 USD 65 billion Arizona commitment to approximately USD 165 billion, with the Phase 3 N2 production target of 2030.
TSMC Kumamoto JASM Fab 1 opened on 24 February 2024 in Kikuyo (菊陽町), Kumamoto Prefecture, as a Sony Semiconductor Solutions / DENSO Corporation / Toyota Motor Corporation joint venture producing 12-nanometre, 16-nanometre, 22-nanometre, and 28-nanometre logic chips with image-sensor packaging integration; JASM Fab 2 ground-breaking occurred in early 2025 targeting 2027 production at 6-nanometre and 7-nanometre nodes. The JASM joint-venture equity architecture as publicly disclosed: TSMC 86.5 per cent, Sony Semiconductor Solutions Corporation 6.0 per cent, DENSO Corporation 5.5 per cent, Toyota Motor Corporation 2.0 per cent [TBD-VERIFY: precise JASM equity composition has been re-stated across multiple cycles; the post-2023 Toyota equity addition produced the current composition]. The Japanese-government subsidy framework — operationalised through the Ministry of Economy, Trade and Industry (METI, 経済産業省) under successive METI Ministers including Yasutoshi Nishimura (西村康稔) and Ken Saito (斎藤健) — provided up to JPY 476 billion subsidy for Fab 1 and up to JPY 732 billion subsidy for Fab 2 [TBD-VERIFY: precise METI subsidy figures vary by reporting cycle]. The Kumamoto-prefectural-government coordination — under Governor Ikuo Kabashima (蒲島郁夫) through 2024 and his successor Takashi Kimura (木村敬) from April 2024 — included land-use, water-supply, electrical-grid, and workforce-housing infrastructure. The 24 February 2024 opening ceremony — attended by TSMC Founder Morris Chang (張忠謀), TSMC Chairman Mark Liu (劉德音), Sony Semiconductor Solutions President Terushi Shimizu (清水照士), DENSO President Koji Arima (有馬浩二), and METI senior leadership — marked the operationalisation of the post-2021 Japan-Taiwan strategic-supply-chain coordination.
TSMC Dresden ESMC (European Semiconductor Manufacturing Company GmbH) ground-breaking occurred on 20 September 2024 with EU Commission President Ursula von der Leyen, German Chancellor Olaf Scholz, Saxony Minister-President Michael Kretschmer, and TSMC CEO C.C. Wei in attendance; the joint-venture equity is TSMC 70 per cent / NXP Semiconductors 10 per cent / Robert Bosch GmbH 10 per cent / Infineon Technologies AG 10 per cent, with target production-start in 2027 at 12-nanometre, 16-nanometre, 22-nanometre, and 28-nanometre nodes serving the European automotive and industrial-electronics customer base. The ESMC Dresden project — operationalised under the EU Chips Act (Regulation (EU) 2023/1781, in force 21 September 2023, the European Union's USD 47 billion-equivalent semiconductor industrial-policy framework) — received German federal-government subsidy of approximately EUR 5 billion, representing approximately 50 per cent of the EUR 10 billion estimated total capital expenditure [TBD-VERIFY: precise German-government subsidy figure; the post-2024 German federal-government budgetary-constraint discussions affected the disbursement schedule]. The site selection in Dresden's "Silicon Saxony" cluster — proximate to Infineon's Dresden facility and the GlobalFoundries Dresden facility — leveraged the post-1990s Saxon semiconductor industrial-ecology and the broader Eastern-German technical-workforce base. The site selection contrasted with the prior 2022–2023 considerations of Italian, Czech, and Hungarian sites that did not produce a viable joint-venture architecture.
The 7 October 2022 / 17 October 2023 / 2 December 2024 progressive BIS (Bureau of Industry and Security) export-control tightening cycle — restricting advanced AI / data-centre chip exports to the PRC, advanced semiconductor manufacturing equipment exports, and through the foreign-direct-product (FDP) rule extending controls to non-US-origin products incorporating US technology — structurally restricted Taiwan-PRC semiconductor-supply-chain flows and operates in interaction with TSMC's global-fab architecture trajectory. The 7 October 2022 rule — the most-significant US export-control action against the Chinese semiconductor industry since the 1990s Wassenaar Arrangement — imposed initial control levels at NVIDIA A100 / H100 performance thresholds and through the FDP rule directly affected TSMC's ability to fabricate certain advanced chips for Chinese fabless designers including HiSilicon. The 17 October 2023 rule expansion tightened the chip-performance thresholds (introducing "Total Processing Performance" / "Performance Density" metrics capturing the NVIDIA A800 / H800 China-tailored chips) and added approximately 13 China-headquartered entities to the Entity List. The 2 December 2024 rule tightened HBM (high-bandwidth-memory) controls relevant to AI-accelerator stacks and added approximately 140 China-headquartered semiconductor entities to the Entity List. Taiwan's compliance architecture — operationalised through the MOEA Bureau of Foreign Trade (國際貿易署, post-September 2023 reorganisation as the International Trade Administration) — established the Taiwan-side strategic-trade-control coordination with US BIS, the Dutch government, and the Japanese government across 2022–2026.
The post-2022 SMIC (Semiconductor Manufacturing International Corporation, 中芯國際) 7-nanometre indigenisation progression, the August 2023 Huawei Mate 60 Pro launch with the Kirin 9000S processor manufactured at SMIC's 7-nanometre node, and the post-2024 Huawei Ascend 910B / 910C AI-accelerator-chip production trajectory constitute the structural evidence on which the empirical debate about the BIS export-control regime's containment efficacy turns. SMIC's 7-nanometre process — initially developed without EUV access through multi-patterning DUV (deep ultraviolet) lithography techniques — represents the most-significant PRC semiconductor-process progression since the post-2014 Big Fund Phase 1 era. The August 2023 Mate 60 Pro launch — disclosed without prior public announcement and confirmed through post-launch teardown analyses by TechInsights and other industry analysts — produced a public-political moment that re-framed the BIS export-control debate. The post-2024 Ascend 910B / 910C trajectory — the Huawei AI-accelerator family targeting NVIDIA H100 / A100 substitution within the PRC market — provided additional evidence that the BIS export-control regime had not fully prevented PRC advanced-process progression, though the yield, cost, and volume profile of the SMIC-Huawei production remained substantially behind the TSMC-produced equivalent. The empirical-debate partition: BIS-hawks framings (Gregory Allen, Sujai Shivakumar) emphasise the containment-success reading; SMIC-progression-empirical framings (TechInsights, certain industry analysts) emphasise the indigenisation-acceleration reading; Carnegie-Mark-Hannah framings emphasise the counter-productive-incentive reading in which the controls accelerated PRC strategic prioritisation of semiconductor self-sufficiency.
The TSMC global-fab architecture's lower-tier complement — UMC (United Microelectronics Corporation, 聯華電子), Vanguard International Semiconductor (世界先進), GlobalWafers (環球晶圓), Powerchip Semiconductor Manufacturing Corporation (力積電), and the memory players Macronix (旺宏電子), Nanya Technology (南亞科技), and Inotera Memories (now part of Micron Memory Taiwan) — operates as the broader Taiwanese semiconductor-industry diaspora architecture extending beyond TSMC's leading-edge concentration. UMC's post-2022 Singapore Pasir Ris Wafer Fab 12i expansion (USD 5 billion announcement, 22-nanometre / 28-nanometre nodes) operationalised the Taiwan-Singapore strategic-supply-chain coordination; Vanguard International Semiconductor's post-2024 Singapore joint-venture with NXP Semiconductors (VisionPower Semiconductor Manufacturing Company, VSMC, announced June 2024) targets 12-inch wafer production by 2027; GlobalWafers' Sherman, Texas, facility (announced June 2022, ground-breaking November 2022, target production 2025) operationalises the silicon-wafer supply-chain US-diversification; Powerchip's joint venture with Tata Group's Tata Electronics for the Dholera (Gujarat, India) semiconductor fab — announced February 2024 with PSMC providing process-technology licensing rather than equity — operationalises the post-2023 India-Taiwan strategic-supply-chain coordination. The lower-tier diaspora's analytical significance: while TSMC's leading-edge architecture dominates the strategic narrative, the broader semiconductor-supply-chain resilience depends on the lower-tier-fab geographic-diversification as much as on the TSMC anchor.
The Taiwan domestic-discourse partition on TSMC's geographic-diversification — the Lai-government "silicon-shield 2.0" affirmative framing versus the KMT-and-TPP-articulated "hollowing out" critique — operates as the principal political-coalition contestation point for the post-2024 Lai-administration semiconductor-diplomacy doctrine. The Lai-government affirmative framing: TSMC's global-fab architecture deepens the cross-Strait deterrence weight by embedding Taiwan-controlled production capacity in the strategic-supply-chain architecture of the United States, Japan, and the European Union, producing reciprocal-political-investment in Taiwan's strategic position. The KMT framing — articulated by KMT Chair Eric Chu (朱立倫), 2024 KMT presidential candidate Hou Yu-ih (侯友宜), and former Kaohsiung Mayor and 2024 KMT vice-presidential candidate Jaw Shaw-kong (趙少康) — emphasises the costs of forced capital-and-talent migration from Taiwan to the United States, framing the post-3 March 2025 Oval-Office pledge as concession under pressure rather than strategic positioning. The TPP framing — articulated by TPP Chair (post-2024) Huang Kuo-chang (黃國昌), former TPP Chair Ko Wen-je (柯文哲) where his pre-2024-detention statements remain on record, and TPP Legislator Lin Kuo-cheng (林國成) — concentrates on the industrial-hollowing critique with emphasis on the long-term-erosion concern. The Han Kuo-yu (韓國瑜) — Legislative Yuan Speaker since February 2024 — opposition-narrative framing has positioned the Lai administration's chip-diplomacy as Taiwan-strategic-asset transfer to the United States with insufficient reciprocal benefit.
The semiconductor-talent-migration question — including the discourse around "30,000+ engineers exported to Arizona / Kumamoto" — is empirically contested but operates as a structuring frame for the post-2024 Taiwan domestic political discourse on TSMC's global-fab architecture. Public statements by MOEA Minister Kuo Jyh-huei (郭智輝), TSMC senior management, and the Taiwan Industrial Development Administration have characterised the talent-migration figures as substantially smaller than the 30,000 frame — with the post-2024 Arizona transferred-engineer count in the low thousands [TBD-VERIFY: precise post-2024 transferred-engineer count from Taiwan to Arizona reported as approximately 2,000–3,000 across 2022–2024, with the post-2024 ramp adding further; some Taiwanese-opposition-framing reporting cited cumulative-over-multi-year figures including indirect-supplier transfers reaching the 30,000+ frame]. The post-2024 cross-Strait talent-flow regulation — operationalised through the Ministry of Labour (勞動部), the National Security Bureau (國家安全局), and the MAC — established the post-2023 Trade Secrets Act (營業秘密法) amendments and the post-2024 National Security Act amendments targeting specific concerns about Taiwanese-semiconductor-engineer recruitment by PRC-headquartered firms. The PRC-side counter-flow architecture — operationalised through SMIC, YMTC, CXMT, and the broader PRC semiconductor industry's recruitment of Taiwanese engineers via Hong Kong intermediaries and Southeast Asian secondment vehicles — produced a sustained 2020–2026 cross-Strait talent-competition dynamic.
The Lai government's MOEA chip-diplomacy doctrine (2024–2026) — operationalised under Minister of Economic Affairs Kuo Jyh-huei (郭智輝, sworn in 20 May 2024) and Vice Minister Chen Cheng-chi (陳正祺) — articulated through the post-March 2025 Seventeen Tasks (十七項任務) framework and the post-2025 Taiwan Industrial Innovation Act (產業創新條例) revision, constitutes the post-2024 strategic-coordination architecture for TSMC's global-fab trajectory and Taiwan's domestic-investment retention. The MOEA chip-diplomacy doctrine's operational dimensions: (a) the post-2024 strategic-coordination with US Department of Commerce, Japanese METI, German Federal Ministry of Economic Affairs and Climate Action (BMWK), and the EU Directorate-General for Communications Networks, Content and Technology (DG CONNECT); (b) the post-2025 Taiwan Industrial Innovation Act revision through the Legislative Yuan introducing additional R&D tax credits and capital-expenditure incentives to retain TSMC's leading-edge investment in Taiwan; (c) the post-2024 talent-retention framework including the post-2023 Act for the Recruitment and Employment of Foreign Professionals (外國專業人才延攬及僱用法) revisions; (d) the post-2025 Kaohsiung Science Park (高雄科學園區) anchor for TSMC's N2 / 2-nanometre and below domestic production. The doctrine's contested reception: DPP framings characterise the doctrine as successful strategic-coordination; KMT and TPP framings emphasise the doctrine's insufficient domestic-investment-retention emphasis.
The post-2022 Pelosi-visit diplomatic-and-semiconductor entanglement, the post-2024 Lai-administration cross-Strait deterrence trajectory, and the post-2025 Trump-2 Oval-Office negotiating-track operate as the integrative strategic-political backdrop within which TSMC's global-fab architecture and Taiwan's chip-diplomacy doctrine are contested. The integrative analytical reading: the post-2020 TSMC global-fab architecture cannot be understood in isolation from the post-2022 Pelosi-visit-anchored cross-Strait crisis trajectory (anchored at TW-C-06), the post-2024 Lai-administration cross-Strait deterrence architecture (anchored at TW-D-02), or the post-2025 Trump-2 negotiating-track architecture (anchored at TW-D-03). The 2–3 August 2022 Pelosi visit and the 4–7 August 2022 PLA exercises occurred within a two-week window of the August 2022 CHIPS Act passage; the post-Lai-inauguration Joint Sword 2024A (May 2024) and Joint Sword 2024B (October 2024) exercises occurred within the same six-month window as the November 2024 TSMC Arizona Fab-21 N4 production start. The integrative trajectory: TSMC's global-fab architecture operates as both a hedge against cross-Strait-conflict scenarios and a coupling-thickening of the US-Japan-EU-Taiwan strategic-economic architecture; the trajectory's deterrence-or-dilution interpretation depends on the political-coalition lens through which it is read.
As of May 2026 — two years into the Lai administration's first term — the post-2020 semiconductor-diaspora architecture is in operational maturation: Arizona Fab-21 Phase 1 N4 production has reached yield parity, Kumamoto JASM Fab 1 is in stable 12–28nm production with Fab 2 in advanced construction, Dresden ESMC ground-work is progressing toward the 2027/2028 production-start target, and the post-March 2025 Trump-Wei Oval-Office Phase 3 N2 trajectory is in early-construction phase. The three-account synthetic reading: (a) the silicon-shield-insurance affirmative reading positions the operational-maturation as the operationalisation of cross-Strait deterrence-thickening through structural-supply-chain coupling; (b) the supply-chain-weakening critique positions the operational-maturation as the structural transfer of Taiwanese strategic-industrial capacity to the United States, Japan, and Europe under post-2024 political-economic pressure; (c) the structural-political-economy reading positions the operational-maturation as the operationalisation of US-China strategic-decoupling in the semiconductor sector, with Taiwan operating as the principal pivot variable and the outcomes contingent on factors largely exogenous to Taiwanese agency. The post-2026 forward-trajectory variables: the post-Section-232 tariff outcome; the post-2026 Taiwan local-elections political-coalition signal; the post-2027 Dresden ESMC and Kumamoto JASM Fab 2 production-start; the post-2028 Arizona Phase 2 N3 production-start; the post-2030 Arizona Phase 3 N2 production-start.

2. The Pre-2020 Architecture and the Origin of the Silicon-Shield Doctrine

2.1 The 1987 Founding and the Hsinchu-Tainan Geographic-Concentration Profile

TSMC's 21 February 1987 incorporation under the laws of the Republic of China was the operational realisation of a developmental-state strategy whose intellectual genealogy traced to the post-1973 first oil crisis and the post-1975 strategic re-orientation under Premier Sun Yun-suan (孫運璿) and Minister Without Portfolio K.T. Li (李國鼎, often anglicised as L.T. Li or rendered as Li Kwoh-ting). Morris Chang (張忠謀, born 1931 in Ningbo, Zhejiang) — Texas Instruments senior executive 1958–1983; General Instrument president 1984–1985 — was recruited by K.T. Li in 1985 as ITRI president and tasked with operationalising the semiconductor-strategic initiative. Chang's 1987 founding architectural choice was the pure-play foundry model: TSMC would build chips designed by external "fabless" customers without competing on chip design.

The 1987–2020 geographic-concentration profile — concentrating leading-edge production at the Hsinchu Science Park (新竹科學園區, established 1980), the Taichung Science Park (台中科學園區, established 2003), and the Tainan Science Park (台南科學園區, established 1996) along a roughly 200-kilometre corridor along Taiwan's western coast — produced the structural concentration that the post-2020 "Silicon Shield" doctrine reflects. By 2020, TSMC's principal production base was concentrated across Fab 12 (Hsinchu, 28-nanometre and below mid-node), Fab 14 / Fab 15 (Tainan, 16-nanometre and 10-nanometre), and Fab 18 (Tainan, 5-nanometre and below) — three principal anchor facilities producing approximately 90 per cent of global advanced-process (sub-10-nanometre) foundry capacity within a 100-kilometre radius. The geographic-concentration profile was the empirical fact on which the post-2000 "Silicon Shield" doctrine rested and the post-2020 geographic-diversification trajectory has begun to alter.

2.2 The Pre-2020 Affirmative and Sceptical Partition on the Silicon-Shield Doctrine

Craig Addison's 2001 Silicon Shield: Taiwan's Protection Against Chinese Attack (Fusion Press) provided the original analytical formulation of the doctrine. The argument: Taiwan's semiconductor centrality, particularly TSMC's anchor positioning in the global integrated-circuit supply chain, imposes such meaningful cost-of-disruption on any PRC military action that the rational-strategic-calculation framework of the PRC leadership would treat the Silicon-Shield deterrence-weight as a material restraint. The 2000s reception of the framing was mixed: in Taiwan, KMT and DPP framings both engaged with the concept though with different emphases; in the United States, the framing was treated cautiously, with Department of Defense and National Security Council analyses noting both the cost-imposition logic and the counter-arguments; in China, the framing was treated with sustained PRC State Council Taiwan Affairs Office and Ministry of Foreign Affairs rejection.

The pre-2020 sceptical readings — articulated by Denny Roy's Taiwan: A Political History (2003); Richard C. Bush's Untying the Knot (2005), Uncharted Strait (2013), and Difficult Choices (2021); and the Bonnie Glaser sustained CSIS commentary — emphasised three concerns: (a) the PRC strategic-calculation hierarchy may prioritise unification as a non-negotiable strategic objective irrespective of economic costs; (b) the conditional contingency: the Silicon-Shield deterrence weight depends on the geographic-concentration profile, which TSMC's then-emerging diversification trajectory could begin to dilute; (c) the substitution risk: even if PRC action damaged Taiwan-located fabs, alternative production at Samsung, Intel, GlobalFoundries, and the China-located SMIC and HSMC fabs might over a multi-year period substitute for some of the disrupted capacity. The pre-2020 affirmative readings concentrated on the cost-imposition logic and the operational-warfare-planning constraint argument.

2.3 The Post-2019 Trump-1 Pressure and the Pre-2020 Strategic-Diversification Inflection

The post-2018 Trump-1 trade-war architecture, the May 2019 Entity List addition of Huawei (with the subsequent 17 August 2020 final foreign-direct-product-rule extension cutting off TSMC's ability to fabricate HiSilicon Kirin chips for Huawei), and the post-2019 deterioration of US-China technology-policy relations established the structural backdrop against which the May 2020 TSMC Phoenix announcement occurred. The Trump-1 administration's pressure on Asian semiconductor producers to "reshore" production — articulated through the Department of Commerce under Secretary Wilbur Ross, the Department of Defense, and the National Security Council — produced the structural-political environment within which TSMC's pre-2020 strategic-diversification calculation was reformulated. The 2018 TSMC Nanjing Fab 16 (28-nanometre and 16-nanometre operation, mainland China) — which by 2020 had operated as TSMC's principal mainland-China production base — became the asymmetric counterpoint to the emerging US-Japan-EU diversification trajectory.

The pre-2020 customer geographic-diversification demand — articulated by Apple, AMD, NVIDIA, Qualcomm, and the broader US fabless-design ecosystem — coupled with the cross-Strait risk profile sharpened by the 2019–2020 Hong Kong protests, produced the operational rationale for TSMC's May 2020 Phoenix announcement. The Tsai administration's coordination — articulated through Premier Su Tseng-chang (蘇貞昌) and Minister of Economic Affairs Wang Mei-hua (王美花) — produced the post-announcement framing of the Phoenix project as Taiwan-strategic positioning rather than capital-and-talent migration. The post-May 2020 strategic-diversification inflection set the trajectory that the post-2022 CHIPS Act, the post-2021 Kumamoto JASM joint venture, and the post-2023 Dresden ESMC joint venture would subsequently operationalise.

3. The Arizona Trajectory — Fab-21 Phase 1 N4 (Nov 2024), Phase 2 N3 (2028), and Phase 3 N2 (2030 / March 2025 USD 100 Billion Pledge)

3.1 The 14 May 2020 Announcement and the Phase 1 Build (2020–2024)

TSMC's 14 May 2020 board-approved press release announced a USD 12 billion initial commitment for a Phoenix, Arizona, 5-nanometre fabrication facility (Fab-21 Phase 1), targeting first-tool-in by 2024 and mass production by 2024. The Phase 1 architecture: the Phoenix facility — designated Fab-21 within TSMC's internal numbering — would replicate the Tainan Fab 18 N5 process at approximately 20,000 wafers-per-month initial capacity; site selection within the Phoenix metropolitan area in North Phoenix, near the intersection of Interstate 17 and Loop 303, leveraged the Arizona semiconductor ecosystem including Intel's Chandler facilities and the broader Arizona semiconductor workforce.

The 2020–2024 Phase 1 build was marked by substantial labour-culture disputes, ASML EUV (extreme ultraviolet) equipment-install delays, construction-cost inflation, and the friction between TSMC-Taiwan management practices and US-Arizona workforce expectations. Reuters, Nikkei Asia, and Bloomberg reporting through 2022–2024 documented the cultural-friction pattern: the long-hours / 24/7 on-call expectations of TSMC-Taiwan fab-floor norms; the construction-labour-shortage challenge; the productivity gap between Taiwan-trained transferred TSMC engineers and US-recruited new hires; and the post-2022 Arizona Pipe Trades Local 469 and Sheet Metal Workers Local 359 negotiating-track activity. The April 2023 announcement that Phase 1 mass production would shift from 2024 to 2025 reflected the construction-and-equipment-installation slippage; the actual N4 (4-nanometre, rather than the originally-announced N5) mass-production commencement in November 2024 reflected the substituted process-technology choice that TSMC's investor communications characterised as a customer-demand-aligned upgrade rather than a delay.

The November 2024 Fab-21 Phase 1 N4 production start — with Apple as the lead announced customer [TBD-VERIFY: December 2024 / January 2025 industry reporting variously cited Apple A16-series and A18-series part numbers as the lead Arizona-fabricated commercial product; TSMC's public language did not disclose precise part-number] — produced the first commercial-volume leading-edge semiconductor production at a TSMC-owned US-located facility. Yield parity between Fab-21 Phase 1 and the Tainan Fab 18 baseline was reported to have approached parity by Q1 2025, though TSMC's quarterly-earnings-call language remained cautious. The November 2024 production-start operated as the operational-baseline event for the post-2024 Arizona-trajectory framing.

3.2 The Phase 2 N3 Expansion (2022 Announcement, 2028 Production Target)

The 9 December 2022 TSMC Phase 2 announcement at the Phoenix Fab-21 "First Tool-In" ceremony — with President Joseph R. Biden in attendance alongside TSMC Founder Morris Chang, TSMC Chairman Mark Liu, TSMC CEO C.C. Wei, Apple CEO Tim Cook, NVIDIA CEO Jensen Huang, and AMD CEO Lisa Su — announced a USD 28 billion Phase 2 commitment covering N3 (3-nanometre) production at a second on-site fab targeting mass production by 2026. The Phase 2 announcement raised the cumulative Phoenix-investment commitment from USD 12 billion to approximately USD 40 billion. The Phase 2 target-production-date framework was subsequently revised across the 2023–2024 reporting cycles: the 2026 original target shifted to 2027 and subsequently to 2028 across the post-2023 TSMC investor disclosures, reflecting the construction-and-equipment-installation realities of the post-2023 phase. The Phase 2 N3 process — replicating the post-2022 Tainan Fab 18 N3 mass-production architecture — targets capacity in the range of 30,000 wafers per month [TBD-VERIFY: precise Phase 2 capacity target varies across TSMC investor communications].

3.3 The Phase 3 N2 Expansion (2024 Announcement, 2030 Production Target, March 2025 USD 100 Billion Pledge)

The 8 April 2024 Phase 3 announcement — coordinated with the CHIPS Office preliminary memorandum of terms (PMT) publication — added a third Phoenix facility covering N2 (2-nanometre) production, raising the cumulative pre-March 2025 announced commitment to approximately USD 65 billion. The Phase 3 N2 process — the most-advanced TSMC node scheduled for the post-2025 mass-production cycle — targets production at the Phoenix site by approximately 2030, with the Hsinchu Fab 20 and Kaohsiung Fab 22 anchoring the Taiwan-side N2 production base from 2025–2026 as the architectural precedent.

The 3 March 2025 Oval-Office announcement by TSMC Chairman C.C. Wei (魏哲家, who succeeded Mark Liu as TSMC Chairman in June 2024 while remaining CEO) of an additional USD 100 billion TSMC US-investment commitment — with President Donald J. Trump and Secretary of Commerce Howard Lutnick in attendance — raised TSMC's cumulative announced US commitment from the pre-March 2025 baseline of approximately USD 65 billion to approximately USD 165 billion. The announced composition included three additional fabrication facilities (covering N2 and beyond), two advanced packaging facilities (relevant to AI-accelerator stacks), and a research and development centre. The political-coalition reception in Taiwan partitioned sharply: DPP framings characterised the announcement as a successful negotiating outcome strengthening Taiwan's strategic-leverage position; KMT and TPP framings characterised the announcement as forced concession draining Taiwanese industrial capacity. Analytical assessments by CSIS (Bonny Lin; Glaser), Brookings (Hass), and Atlantic Council (Sung Wen-Ti) raised the methodological question of whether the USD 100 billion represented genuinely additional investment or the relabelling of capital expenditure already in TSMC's multi-year strategic plan.

3.4 The CHIPS Act Conditionality Framework and the Trump-2 Redirection Threat

The 15 November 2024 Biden CHIPS Office final-grant award of USD 6.6 billion to TSMC Arizona — preceded by the 8 April 2024 preliminary memorandum of terms — was finalised in the post-election lame-duck transition window as part of a CHIPS-Office "race-to-finalize" sequence. The CHIPS Office's standard grant-notice framework imposed: (a) a profit-share clawback obligation; (b) an R&D-facility obligation requiring recipients to operate material R&D activities in the United States; (c) a childcare-provision obligation for employees of large grant projects; (d) a stock-buyback restriction; (e) the "guardrails" prohibition on material expansion of advanced semiconductor capacity in "foreign countries of concern" (operatively, the PRC) for ten years, with "legacy" semiconductor capacity treated under a separate framework.

The post-20 January 2025 Trump-2 administration's signalled scepticism of the CHIPS Act's subsidy architecture — articulated through President Trump's October 2024 Joe Rogan podcast appearance disparaging the CHIPS Act as "bad" and suggesting tariffs as the appropriate alternative, and through the post-inauguration White House press-pool exchanges — produced the post-March 2025 redirection-threat concern within the TSMC investor-and-analyst community. The 3 March 2025 Oval-Office Wei-Trump announcement operated as the post-CHIPS-Act-conditionality reframing of the TSMC-US relationship: the additional USD 100 billion commitment was characterised as not contingent on additional CHIPS Act subsidy, with the underlying political-economic substitution of subsidy-and-conditionality (Biden-era) for tariff-and-pressure (Trump-2) operating as the structural transition. The post-March 2025 trajectory remains contested across the post-inauguration first-year window, with the Section 232 semiconductor investigation (initiated 1 April 2025) producing the principal post-March 2025 regulatory variable.

4. The Kumamoto Trajectory — JASM Fab 1 (Feb 2024 Open), JASM Fab 2 (2027 Target), and the Sony-DENSO-Toyota Joint-Venture Architecture

4.1 The 2021 JASM Announcement and the Japan-Taiwan Strategic-Supply-Chain Coordination

TSMC's November 2021 announcement of the Kumamoto Prefecture, Japan, fabrication facility — operationalised through the Japan Advanced Semiconductor Manufacturing (JASM, 日本先端半導體製造株式會社) joint venture with Sony Semiconductor Solutions Corporation — represented the first TSMC overseas fabrication facility announced since the 14 May 2020 Phoenix announcement and the structural origin of the post-2021 Japan-Taiwan strategic-supply-chain coordination. The joint-venture initial equity architecture: TSMC 86.5 per cent, Sony Semiconductor Solutions Corporation 6.0 per cent, with DENSO Corporation (the Toyota-affiliated automotive electronics supplier) joining in February 2022 as a minority equity holder at 5.5 per cent, and Toyota Motor Corporation joining in late 2023 at 2.0 per cent producing the current post-2024 four-party equity composition [TBD-VERIFY: precise post-2024 JASM equity composition has been variously reported; the post-Fab-2 announcement in early 2025 added additional capital but did not materially alter the equity proportions].

The Japan-Taiwan strategic-supply-chain coordination context: the post-2020 Japanese government's recognition of semiconductor-supply-chain dependency vulnerability — articulated through the post-2020 Suga Yoshihide (菅義偉) cabinet's Strategy for Semiconductors and Digital Industry (半導体・デジタル産業戦略) and the post-2021 Kishida Fumio (岸田文雄) cabinet's continuation framework — provided the political-economic context. The post-2020 METI Minister Yasutoshi Nishimura (西村康稔) coordinated the Japanese-government subsidy framework, providing initial Fab 1 subsidy of up to JPY 476 billion (approximately USD 3.5 billion at the then-prevailing exchange rate) representing approximately 40 per cent of the estimated Fab 1 capital expenditure. The METI subsidy framework — operationalised through the post-2021 amended Strategic Industries Special Measures Act (特定半導体生産施設整備等計画認定) — established the legal-regulatory architecture for the JASM project.

4.2 The 24 February 2024 JASM Fab 1 Opening and the 12–28nm Production Architecture

The 24 February 2024 JASM Fab 1 opening ceremony in Kikuyo (菊陽町), Kumamoto Prefecture, marked the operationalisation of the post-2021 Japan-Taiwan strategic-supply-chain coordination. Attendees included TSMC Founder Morris Chang (張忠謀), TSMC Chairman Mark Liu (劉德音, in his final months as chairman before the June 2024 transition to C.C. Wei), Sony Semiconductor Solutions President Terushi Shimizu (清水照士), DENSO President Koji Arima (有馬浩二), METI senior leadership, Kumamoto Prefecture Governor Ikuo Kabashima (蒲島郁夫, in his final months before April 2024 transition to Takashi Kimura (木村敬)), and Kikuyo Mayor Yoichi Yoshimoto (吉本孝壽). The ceremony — held approximately 23 months after the November 2021 announcement — established the fastest TSMC overseas-fab build-to-opening timeline in TSMC's history, contrasting with the Phoenix Phase 1 build's 2020–2024 timeline.

The Fab 1 production architecture: 12-nanometre, 16-nanometre, 22-nanometre, and 28-nanometre logic-chip production targeting approximately 55,000 wafers-per-month capacity at full ramp [TBD-VERIFY: precise post-2024 JASM Fab 1 capacity figures]. The production-customer architecture concentrated on Sony image-sensor packaging integration (Sony's CMOS image sensors used in the post-2020 Apple iPhone, Samsung Galaxy, and broader mobile-device ecosystem are produced through a TSMC-fabricated logic-chip backbone with Sony's image-sensor stacking), DENSO's automotive-electronics requirements (post-2020 automotive-semiconductor demand surge produced by the post-2020 vehicle-electrification trajectory), and Toyota's strategic-supply-chain coordination. The geographic-significance of the Kumamoto site selection: the post-2020 strategic-supply-chain considerations of geographic-diversification within Japan (away from the post-2011 Tohoku-disaster-affected northeastern region; toward the southwestern Kyushu region with proximity to Taiwan and the post-2020 Japan-Taiwan strategic-supply-chain coordination architecture); the Kyushu region's existing semiconductor-industry ecosystem (Sony's Kumamoto image-sensor facility; Mitsubishi Electric's Kumamoto power-semiconductor facility); the favourable water-supply and electrical-grid infrastructure.

4.3 The Post-2024 JASM Fab 2 Ground-Breaking and the 6–7nm Production Trajectory

The post-February 2024 JASM Fab 2 announcement — finalised in late 2024 with the formal ground-breaking in early 2025 [TBD-VERIFY: precise Fab 2 ground-breaking date in late 2024 / early 2025] — extends the Kumamoto architecture to 6-nanometre and 7-nanometre production targeting 2027 mass production. The Fab 2 capital expenditure of approximately JPY 1.8 trillion (approximately USD 12 billion) — together with the Fab 1 JPY 1.1 trillion capital expenditure — produces a cumulative Kumamoto commitment of approximately JPY 2.9 trillion (approximately USD 19 billion). The Japanese-government subsidy framework for Fab 2 — up to JPY 732 billion (approximately USD 5 billion) — represents approximately 40 per cent of the Fab 2 estimated capital expenditure, maintaining the post-2021 Japanese-government subsidy-share framework. The Fab 2 production trajectory targets the post-2027 European, North American, and Asian customer-base demand for 6-nanometre and 7-nanometre logic chips, particularly the automotive-electronics and AI-accelerator stacks.

4.4 The Kumamoto Trajectory's Cross-Strait and US-Japan Strategic Significance

The Kumamoto trajectory's cross-Strait strategic significance: the post-2024 Japan-Taiwan strategic-supply-chain coordination operates as the principal Indo-Pacific complement to the post-2020 US-Taiwan industrial-policy coordination. The post-2021 Kishida administration's Strategy for Semiconductors and Digital Industry and the post-2024 Ishiba Shigeru (石破茂) administration's continuation framework establish the Japanese-government strategic-political backing for the Kumamoto trajectory. The post-2024 Japan-Taiwan-US trilateral semiconductor coordination — operationalised through the post-2022 Chip 4 (US-Japan-South Korea-Taiwan) framework and the post-2024 quadrilateral semiconductor coordination — establishes the broader strategic architecture. The Kumamoto trajectory's empirical contribution to the silicon-shield doctrine: TSMC's Japan-located production capacity at 6–28nm provides the substantial geographic-diversification of TSMC's lower-leading-edge production capacity, complementing the post-2024 Arizona architecture's leading-edge concentration. The political-economic significance: the post-2024 Japan-Taiwan strategic-supply-chain coordination operates without the same political-coalition contestation in Taiwan that the post-2024 Trump-2 Arizona trajectory produces; the Kumamoto framing in Taiwanese domestic discourse is substantially affirmative across both DPP and KMT framings.

5. The Dresden Trajectory — ESMC Ground-Breaking (Sep 2024), the EU Chips Act, and the NXP-Bosch-Infineon Joint-Venture Architecture

5.1 The 2023 ESMC Announcement and the EU Chips Act Framework

TSMC's 8 August 2023 announcement of the European Semiconductor Manufacturing Company (ESMC GmbH) joint venture — operationalised with NXP Semiconductors (Netherlands-headquartered automotive-and-industrial-electronics semiconductor producer), Robert Bosch GmbH (German automotive supplier), and Infineon Technologies AG (German power-and-industrial-electronics semiconductor producer) — represented TSMC's first European-located fabrication facility and the structural origin of the post-2023 EU-Taiwan strategic-supply-chain coordination. The joint-venture equity architecture: TSMC 70 per cent, NXP 10 per cent, Bosch 10 per cent, Infineon 10 per cent. The site selection in Dresden, Saxony (Sachsen), leveraged the post-1990s "Silicon Saxony" cluster including Infineon's Dresden facility (since 1995), the GlobalFoundries Dresden facility (since 1999), and the broader Eastern-German technical-workforce base.

The EU Chips Act framework: Regulation (EU) 2023/1781, in force 21 September 2023, the European Union's USD 47 billion-equivalent semiconductor industrial-policy framework consisting of three pillars (the Chips for Europe Initiative R&D pillar; the Framework for Security of Supply manufacturing pillar including provisions for "first-of-a-kind" facility designation; the Crisis Mechanism monitoring pillar). The post-2023 EU Chips Act's manufacturing pillar — operationalised through the European Chips Joint Undertaking and the EU Commission's Important Project of Common European Interest (IPCEI) designation framework — provided the legal-regulatory architecture for state-aid clearance of the German federal-government subsidy to ESMC. The German federal-government subsidy of approximately EUR 5 billion — representing approximately 50 per cent of the EUR 10 billion estimated total capital expenditure — required EU Commission state-aid clearance, which was issued on 20 August 2024 through the formal State Aid Notice procedure.

5.2 The 20 September 2024 ESMC Ground-Breaking Ceremony

The 20 September 2024 ESMC ground-breaking ceremony in Dresden marked the operationalisation of the post-2023 EU-Taiwan strategic-supply-chain coordination. Attendees included: European Commission President Ursula von der Leyen; German Chancellor Olaf Scholz; Federal Minister of Economic Affairs and Climate Action Robert Habeck (Greens); Saxony Minister-President Michael Kretschmer (CDU); Dresden Mayor Dirk Hilbert (FDP); TSMC CEO C.C. Wei (魏哲家, by then also Chairman following the June 2024 Mark Liu transition); NXP CEO Kurt Sievers; Bosch CEO Stefan Hartung; Infineon CEO Jochen Hanebeck; and Taiwanese Minister of Economic Affairs Kuo Jyh-huei (郭智輝, sworn in 20 May 2024 under the new Lai administration). The ceremony — held approximately 13 months after the August 2023 announcement and approximately one month after the August 2024 EU state-aid clearance — established the post-2024 Lai-administration first major chip-diplomacy operational milestone.

The Dresden site's production architecture: 12-nanometre, 16-nanometre, 22-nanometre, and 28-nanometre logic-chip production targeting approximately 40,000 wafers-per-month capacity at full ramp [TBD-VERIFY: precise post-2024 ESMC Dresden capacity targets]. The production-customer architecture concentrates on European automotive-electronics demand (Bosch and Infineon are principal automotive-electronics customers; the post-2020 European vehicle-electrification trajectory produces sustained 22–28nm logic-chip demand), industrial-electronics demand (Infineon's industrial-electronics product lines), and automotive-Internet-of-Things adjacent applications (NXP's automotive-connectivity product lines). The target production-start of 2027 — with the post-2027 ramp toward 2028 full-volume — places ESMC Dresden as the third TSMC overseas-fab to commence commercial production after Arizona Phase 1 (November 2024) and Kumamoto Fab 1 (February 2024).

5.3 The Pre-2023 Site-Selection Alternatives and the Dresden Choice

The pre-2023 TSMC European site-selection considerations across 2021–2023 evaluated alternative locations including: an Italian site (with Italian government engagement during the post-2021 Draghi government and the subsequent post-2022 Meloni government, but failing to converge on viable joint-venture architecture); a Czech site (with Czech government engagement but limited semiconductor-ecosystem depth); a Hungarian site (with Hungarian government engagement but limited automotive-electronics-customer base). The Dresden choice reflected: (a) the existing Silicon Saxony semiconductor-industry ecosystem providing the principal labour-supply and supplier-network advantage; (b) the proximity to NXP, Bosch, and Infineon European headquarters and major operations; (c) the German federal-government's substantial subsidy capacity and the post-2021 Ampelkoalition (SPD-Greens-FDP) coalition's strategic-industrial-policy backing under Chancellor Scholz; (d) the post-2022 Russian-Ukraine-war-induced acceleration of European strategic-supply-chain considerations; (e) the post-2023 Saxon state-government's coordinated site-readiness package including land, water-supply, and electrical-grid infrastructure.

5.4 The Dresden Trajectory's Strategic Significance and the Post-2024 EU-Taiwan Coordination

The Dresden trajectory's strategic significance: the post-2024 EU-Taiwan strategic-supply-chain coordination operates as the principal European complement to the post-2020 US-Taiwan and the post-2021 Japan-Taiwan industrial-policy coordination architectures. The post-2024 ESMC Dresden project — together with the post-2022 STMicroelectronics-Intel ITRP project in Catania, Sicily, and the post-2023 Wolfspeed-ZF Friedrichshafen silicon-carbide power-semiconductor facility — establishes the European-located leading-edge semiconductor-manufacturing architecture. The political-economic significance: the post-2024 EU-Taiwan strategic-supply-chain coordination operates within the broader post-2022 EU strategic-autonomy framework articulated through the Strategic Compass, the EU Chips Act, and the post-2024 European Defence Industrial Strategy. The Dresden trajectory's contestation in Taiwanese domestic discourse: substantially less contested than the post-2024 Arizona Phase 3 N2 / USD 100 billion pledge architecture, with DPP and KMT framings both broadly affirmative of the post-2023 EU-Taiwan strategic-coordination trajectory.

6. The BIS Export-Control Tightening Cycle and Taiwan's Compliance Architecture (Oct 2022 / Oct 2023 / Dec 2024)

6.1 The 7 October 2022 BIS Rule and the Foreign-Direct-Product-Rule Extension

The 7 October 2022 BIS (Bureau of Industry and Security) export-control rule — issued by the US Department of Commerce under Secretary Gina Raimondo with Under Secretary for Industry and Security Alan Estevez — constituted the most-significant US export-control action against the Chinese semiconductor industry since the 1990s Wassenaar Arrangement. The rule's principal restrictions: (a) the export of advanced AI / data-centre chips, with initial control levels at NVIDIA A100 / H100 performance thresholds defined through the Advanced Computing Foreign-Direct-Product-Rule (Advanced Computing FDP); (b) the export of advanced semiconductor manufacturing equipment, particularly DUV (deep ultraviolet) lithography below specified node thresholds (initially 14-nanometre and below for logic chips); (c) through the foreign-direct-product rule, the extension of controls to non-US-origin products incorporating US technology — directly affecting TSMC's ability to fabricate certain advanced chips for Chinese fabless designers including HiSilicon. The rule's Entity-List additions included 31 China-headquartered entities including YMTC (Yangtze Memory Technologies Corporation) and additional SMIC subsidiaries.

6.2 The 17 October 2023 BIS Rule Expansion

The 17 October 2023 BIS rule expansion — issued exactly one year after the 7 October 2022 rule — tightened the chip-performance thresholds by introducing the "Total Processing Performance" (TPP) and "Performance Density" (PD) metrics replacing the prior interconnect-bandwidth metric. The TPP-and-PD metrics captured NVIDIA's post-2022 A800 / H800 China-tailored chips that had been engineered to fall just below the October 2022 controls' interconnect-bandwidth thresholds while maintaining substantial AI-training capability. The October 2023 rule added approximately 13 China-headquartered entities to the Entity List and introduced additional "country group" controls capturing third-country diversion routes including Macao, the United Arab Emirates, and certain Central Asian jurisdictions. The 17 October 2023 rule also tightened semiconductor-manufacturing-equipment controls and expanded the application of the foreign-direct-product rule.

6.3 The 2 December 2024 BIS Rule and the HBM Controls

The 2 December 2024 BIS rule (the "December 2" rule) — issued in the post-5 November 2024 election lame-duck transition window — tightened HBM (high-bandwidth-memory) controls relevant to AI-accelerator stacks and added approximately 140 China-headquartered semiconductor entities to the Entity List. The HBM controls — restricting the export of HBM2E, HBM3, and HBM3E memory products to PRC customers — directly affected the AI-accelerator-stack architecture (HBM is integrated with leading-edge AI-accelerator processors in 2.5D / 3D packaging configurations). The 140-entity additions included additional SMIC subsidiaries, YMTC affiliates, CXMT-adjacent suppliers, and a substantial cohort of post-2022 PRC semiconductor-equipment domestic producers including Naura Technology Group, AMEC (Advanced Micro-Fabrication Equipment Inc.), and ACM Research Shanghai. The December 2024 rule operated as the final pre-Trump-2 BIS rule and established the regulatory-architecture baseline against which the post-January 2025 Trump-2 BIS rule-making activity would be evaluated.

6.4 Taiwan's Compliance Architecture and the Indirect-Export Loophole Discourse

Taiwan's compliance architecture — operationalised through the MOEA International Trade Administration (國際貿易署, post-September 2023 reorganisation of the Bureau of Foreign Trade) under successive Director-Generals Cynthia Kiang (江文若) and Roy Lee (李淳, post-2024) — established the Taiwan-side strategic-trade-control coordination with the US BIS, the Dutch government, and the Japanese government across 2022–2026. The Taiwan-side architecture: post-2022 amendments to the Strategic High-Tech Commodities Import and Export Control Regulations (戰略性高科技貨品輸出入管理辦法) under the Foreign Trade Act (貿易法); the post-2023 enhanced end-user-verification requirements for semiconductor-product and semiconductor-manufacturing-equipment exports to designated jurisdictions; the post-2024 strategic-trade-control list expansion to align with the US BIS Entity List additions.

The indirect-export-via-Hong-Kong and mainland-subsidiary loophole discourse: post-2022 reporting and analysis (Nikkei Asia, Reuters, Bloomberg, the post-2023 US Government Accountability Office (GAO) reports) documented persistent diversion patterns including (a) Hong Kong-based intermediary firms purchasing semiconductor products and re-exporting to mainland PRC end-users; (b) Taiwanese-firm mainland subsidiaries (including the post-2018 TSMC Nanjing Fab 16 operation) supplying products that incorporate technology that would be restricted if exported directly from Taiwan; (c) Southeast Asian (Vietnamese, Malaysian, Indonesian) and Central Asian (Kazakhstan, Kyrgyzstan) intermediary diversion patterns. The post-2024 Taiwan-side compliance enhancements included additional end-user-verification requirements for Hong Kong-routed transactions and enhanced cooperation with US BIS on cross-jurisdictional diversion-detection. The ASML EUV machine sales restrictions — operationalised through the Dutch government's post-September 2023 export-control coordination — restricted EUV machine sales to SMIC, Hua Hong Semiconductor, and other PRC customers, with the post-2024 DUV restrictions tightened across the post-2024 cycle.

7. The PRC Semiconductor-Indigenisation Progression — SMIC 7nm, Huawei Ascend, and the Asymmetric Response

7.1 The Post-2022 SMIC 7-Nanometre Indigenisation Progression

SMIC's (Semiconductor Manufacturing International Corporation, 中芯國際) post-2022 7-nanometre process development — initially documented in TechInsights teardown analysis of the post-2022 MinerVa Bitcoin-mining ASIC product produced at SMIC — represented the most-significant PRC semiconductor-process progression since the post-2014 Big Fund Phase 1 era. The SMIC 7-nanometre process — developed without EUV (extreme ultraviolet) lithography access through multi-patterning DUV (deep ultraviolet) lithography techniques — operated as the empirical demonstration that the PRC semiconductor industry could partially circumvent the BIS export-control regime through alternative process-engineering pathways. The 7-nanometre process's yield, cost, and volume profile remained substantially behind the TSMC-produced equivalent through 2024–2025, but the existence of commercial-volume production at 7-nanometre represented a structural inflection in the PRC semiconductor-indigenisation trajectory.

7.2 The August 2023 Huawei Mate 60 Pro and the Kirin 9000S Processor

The 29 August 2023 Huawei Mate 60 Pro launch — disclosed without prior public announcement and timed to coincide with US Commerce Secretary Gina Raimondo's official visit to Beijing — produced a public-political moment that re-framed the BIS export-control debate. The Mate 60 Pro's Kirin 9000S processor — confirmed through post-launch teardown analyses by TechInsights and other industry analysts as manufactured at SMIC's 7-nanometre node — represented the first commercial-volume Huawei flagship-smartphone processor manufactured at an advanced-process node since the post-2020 BIS foreign-direct-product-rule extension cut off TSMC's ability to fabricate HiSilicon Kirin chips for Huawei. The Mate 60 Pro launch produced sustained 2023–2024 PRC-side political-economic discourse framing the post-2020 BIS export-control regime as having accelerated rather than restrained Chinese semiconductor indigenisation. The US-side discourse partition: BIS-hawks framings (Allen, Shivakumar) characterised the SMIC 7-nanometre progression as expected but not the structural-threat reading that the PRC-side narrative implied; counter-framings (certain Cato Institute, Carnegie Mark Hannah, and academic-economist analyses) characterised the SMIC progression as evidence of counter-productive incentive structures in the post-2020 export-control regime.

7.3 The Post-2024 Huawei Ascend 910B / 910C AI-Accelerator-Chip Trajectory

The post-2024 Huawei Ascend 910B / 910C AI-accelerator-chip family — Huawei's strategic-response architecture to the post-2022 BIS restrictions on NVIDIA A100 / H100 / A800 / H800 / H20 exports to the PRC — operates as the principal post-2024 PRC AI-accelerator-stack architecture. The Ascend 910B — produced at SMIC's 7-nanometre node with HBM2 / HBM2E memory integration sourced through CXMT-and-pre-December-2024-export-controls Samsung / SK Hynix supply — operated as the post-2023 commercial-volume substitute for NVIDIA A100 / A800 in the PRC market. The Ascend 910C — the post-2024 announced successor with enhanced performance — targets NVIDIA H100 / H800 / H20 substitution within the PRC market and is in early-volume production at SMIC's 7-nanometre node with the post-2025 production ramp. The 2024–2025 Ascend production-volume profile [TBD-VERIFY: precise post-2024 Ascend 910B / 910C production-volume figures vary across industry analyst estimates, with the TechInsights, IC Insights, and TrendForce estimates ranging from low hundreds of thousands to single-digit millions of units].

7.4 The 2024 Big Fund Phase 3 and the PRC Semiconductor-Industrial-Policy Architecture

The May 2024 announcement of the National Integrated Circuit Industry Investment Fund Phase 3 (大基金三期) — with registered capital of RMB 344 billion (approximately USD 47.5 billion at then-prevailing exchange rates) — represented the largest single-tranche PRC semiconductor-industrial-policy commitment to date, exceeding the combined Phase 1 (RMB 138.7 billion, 2014) and Phase 2 (RMB 204.1 billion, 2019) capitalisations. The Big Fund Phase 3's strategic-investment focus: equipment-supplier domestication (Naura, AMEC, ACM Shanghai); advanced-process indigenisation (SMIC, Hua Hong Semiconductor); memory-product capacity (YMTC, CXMT); and the post-2024 AI-accelerator and HBM domestic-production trajectory. The Big Fund Phase 3 operates within the broader post-2024 "new productive forces" (新质生产力) framework articulated by Xi Jinping at the March 2024 National People's Congress and re-articulated at the 2025 and 2026 Two Sessions (anchored at CN-D-04). The empirical-debate partition on the PRC semiconductor-industrial-policy efficacy: the post-2024 SMIC, YMTC, and CXMT progression-evidence provides material for both the indigenisation-acceleration reading (PRC industrial policy is succeeding) and the productivity-gap reading (PRC indigenous capacity remains substantially behind the leading-edge US, Japan, EU, Taiwan, South Korea producers).

8. The Taiwan Domestic-Expansion Balance — Hsinchu / Tainan / Kaohsiung and the Industrial Innovation Act Revision

8.1 The Post-2020 Domestic-Expansion Architecture

The post-2020 TSMC domestic-expansion architecture — operating in parallel to the Arizona, Kumamoto, and Dresden diaspora trajectory — concentrates leading-edge production capacity in the Hsinchu, Taichung, Tainan, and (post-2023) Kaohsiung Science Park anchors. The post-2020 capital-expenditure trajectory: TSMC's annual capital expenditure reached approximately USD 30–32 billion in 2022 and approximately USD 30 billion in 2023; the post-2024 capital-expenditure guidance was approximately USD 32–36 billion for 2024 and approximately USD 38–42 billion for 2025 [TBD-VERIFY: precise post-2024 TSMC annual capital-expenditure figures]. The substantial majority of the post-2024 capital-expenditure flow continued to be Taiwan-allocated, with the Arizona / Kumamoto / Dresden combined receiving approximately 20–25 per cent of the post-2024 capital-expenditure flow [TBD-VERIFY: precise Taiwan-versus-overseas capital-expenditure allocation ratios across 2024–2025 vary across TSMC investor disclosures and analyst reports].

The Hsinchu Fab 20 N2 (2-nanometre) production anchor — targeted for mass production in late 2025 — operationalises the post-2024 leading-edge production base in Taiwan. The Tainan Fab 18 N3 (3-nanometre) mass production — commenced Q4 2022 and ramping through 2023–2025 — continues to anchor the post-2024 3-nanometre production base. The Kaohsiung Science Park (高雄科學園區) Fab 22 — announced in 2021 and ground-broken in 2022 — concentrates the post-2026 N2 production capacity expansion. The post-2024 Kaohsiung anchor represents the geographic-diversification of TSMC's domestic production base beyond the historical Hsinchu / Tainan concentration, with the Kaohsiung site selection partially driven by the post-2020 strategic-supply-chain considerations of intra-Taiwan geographic-diversification.

8.2 The Post-2025 Industrial Innovation Act Revision

The post-2025 Industrial Innovation Act (產業創新條例) revision through the Legislative Yuan — operationalised under MOEA Minister Kuo Jyh-huei (郭智輝) and the Executive Yuan under Premier Cho Jung-tai (卓榮泰) — introduced additional R&D tax credits and capital-expenditure incentives targeting retention of TSMC's leading-edge investment in Taiwan. The revision's principal provisions: (a) the extension of the post-2023 "Article 10-2" leading-edge R&D tax-credit framework (the so-called "Taiwan Chips Act" framing in domestic Taiwanese discourse) — which provides a 25 per cent R&D tax credit and a 5 per cent equipment-investment tax credit to qualifying Taiwanese semiconductor and high-technology firms — to additional process-technology categories; (b) the post-2025 amended thresholds for qualifying R&D expenditure; (c) the post-2025 enhanced equipment-purchase tax-credit framework. The post-2025 revision was passed through the Legislative Yuan in [TBD-VERIFY: specific Legislative Yuan passage date for the post-2025 Industrial Innovation Act revision] with cross-coalition support across DPP, KMT, and TPP positions reflecting the broad political-consensus on the industrial-retention objective.

8.3 The Domestic-Expansion-Versus-Diaspora Political-Coalition Discourse

The domestic-expansion-versus-diaspora political-coalition discourse in Taiwan: the DPP framing emphasises the dual-track nature of TSMC's post-2020 trajectory, with the domestic-expansion (Hsinchu / Tainan / Kaohsiung) and the diaspora (Arizona / Kumamoto / Dresden) operating as mutually-reinforcing components of the post-2020 silicon-shield-2.0 architecture. The KMT framing emphasises the long-term industrial-base-erosion concern, framing the post-2024 trajectory as risking the post-2020s erosion of Taiwan's semiconductor-industry concentration through forced capital-and-talent migration. The TPP framing emphasises the post-2024 political-coalition's industrial-hollowing critique with particular attention to the post-3 March 2025 Oval-Office pledge. The empirical-evidence partition: the post-2024 capital-expenditure flow continues to be majority-Taiwan-allocated, supporting the DPP dual-track framing; but the post-2024 strategic-political pressure continues to operate as the principal post-2024 variable for the long-term retention question.

9. The Lower-Tier Fab Architecture — UMC, Vanguard, GlobalWafers, Powerchip, and the PSMC-Tata Dholera JV

9.1 UMC and the Singapore Pasir Ris Expansion

United Microelectronics Corporation (UMC, 聯華電子) — Taiwan's second-largest foundry after TSMC, founded in 1980 as a spin-out from ITRI — operates principal production facilities in Hsinchu (Fab 8A, 8B, 8C, 8D, 8E, 8F), Tainan (Fab 12A), and Singapore (Fab 12i). UMC's post-2022 Singapore Pasir Ris Wafer Fab 12i expansion — a USD 5 billion announcement covering 22-nanometre and 28-nanometre nodes — operationalised the Taiwan-Singapore strategic-supply-chain coordination and provides the principal UMC overseas-capacity expansion of the post-2020 cycle. The Singapore expansion's strategic significance: Singapore's longstanding semiconductor-industry ecosystem (since the 1970s), the favourable political-stability profile, and the proximity to Southeast Asian end-customer markets. The Singapore expansion targets the post-2025 / 2026 production ramp.

9.2 Vanguard International Semiconductor and the VSMC Joint Venture

Vanguard International Semiconductor (世界先進積體電路) — the TSMC-affiliated mid-node foundry — announced in June 2024 a joint venture with NXP Semiconductors named VisionPower Semiconductor Manufacturing Company (VSMC) targeting Singapore-located 12-inch wafer production at the 130-nanometre to 40-nanometre nodes by 2027. The joint-venture equity: Vanguard 60 per cent / NXP 40 per cent [TBD-VERIFY: precise VSMC equity composition]. The total VSMC capital expenditure: approximately USD 7.8 billion through the post-2024 build-out cycle. The VSMC project's strategic significance: the Vanguard-NXP coordination operates as the second principal Singapore-located joint venture (alongside UMC's Pasir Ris expansion) and demonstrates the post-2024 Singapore-anchored Southeast Asian semiconductor-supply-chain coordination.

9.3 GlobalWafers and the Silicon-Wafer Supply-Chain Geographic-Diversification

GlobalWafers Co., Ltd. (環球晶圓) — the world's third-largest silicon-wafer producer after Shin-Etsu Chemical (Japan) and SUMCO (Japan) — operates the principal Taiwanese-headquartered silicon-wafer architecture. GlobalWafers' post-2022 Sherman, Texas, facility — announced June 2022, ground-breaking November 2022, target production 2025 — operationalises the silicon-wafer supply-chain US-diversification. The Sherman facility's strategic significance: the post-2022 CHIPS Act semiconductor-industrial-policy framework supports silicon-wafer production as upstream of the leading-edge foundry architecture; the Sherman facility represents the first US-located new silicon-wafer fabrication capacity since the 1990s. The post-2022 GlobalWafers Sherman facility received CHIPS Act subsidy of approximately USD 400 million in the post-2024 announcement cycle [TBD-VERIFY: precise GlobalWafers Sherman CHIPS Act subsidy figure].

9.4 Powerchip and the PSMC-Tata Dholera Joint Venture

Powerchip Semiconductor Manufacturing Corporation (PSMC, 力積電) — Taiwan's third-tier foundry after TSMC and UMC, operating principal facilities in Hsinchu and Miaoli — provides process-technology licensing to the post-2024 Tata Electronics Dholera (Gujarat, India) semiconductor fab. The February 2024 Tata Group announcement of the Dholera fab — operationalised with PSMC providing process-technology licensing rather than equity participation — represents the post-2023 India-Taiwan strategic-supply-chain coordination's principal operational milestone. The Dholera project's targeted production architecture: 28-nanometre, 40-nanometre, 65-nanometre, and 130-nanometre logic-chip production targeting approximately 50,000 wafers-per-month capacity at full ramp [TBD-VERIFY: precise Dholera capacity targets]. The total Dholera capital expenditure: approximately USD 11 billion, with Indian-federal-government and Gujarat-state-government subsidy providing approximately 50 per cent of the total. The post-2024 ground-breaking and the post-2026 production-start trajectory operationalise the post-2023 India semiconductor-industrial-policy framework (the India Semiconductor Mission and the Semicon India Programme).

9.5 The Memory Players — Macronix, Nanya Technology, and Inotera

The Taiwanese memory-product architecture: Macronix International Co., Ltd. (旺宏電子) — the principal Taiwanese NOR flash and ROM producer, headquartered in Hsinchu; Nanya Technology Corporation (南亞科技) — the principal Taiwanese DRAM producer affiliated with the Formosa Plastics Group, headquartered in Taoyuan; and Inotera Memories, Inc. (華亞科技) — formerly a Nanya-Micron joint venture, now operating as Micron Memory Taiwan following the 2016 Micron-led acquisition. The post-2024 memory-architecture trajectory: Nanya Technology's post-2022 1A-nanometre and 1B-nanometre DRAM process-technology progression; Macronix's post-2022 NOR flash and 3D NAND development; and Micron Memory Taiwan's post-2022 1-alpha / 1-beta / 1-gamma DRAM process ramp at the Taichung and Taoyuan facilities. The post-2024 Taiwanese memory-architecture operates in parallel to the SK Hynix and Samsung Korean-headquartered memory-architecture and the YMTC / CXMT PRC-headquartered memory-architecture as the principal global memory-product supplier-base.

9.6 The Equipment-Supplier Hub Architecture

The semiconductor-equipment-supplier hub architecture — Applied Materials, Inc. (US-headquartered), Lam Research Corporation (US-headquartered), KLA Corporation (US-headquartered), Tokyo Electron Ltd. (Japan-headquartered), Hitachi High-Tech Corporation (Japan-headquartered), and ASML Holding NV (Netherlands-headquartered) — operates the principal global semiconductor-manufacturing-equipment supplier base. The post-2022 BIS export-control regime's restrictions on equipment exports to the PRC — operationalised through coordinated US-Dutch-Japanese export-control measures in the post-September 2023 framework — produced sustained 2022–2026 China-customer revenue declines at the equipment-supplier hub. The equipment-supplier hub's Taiwan exposure: TSMC's leading-edge fab buildout in Taiwan and at the Arizona / Kumamoto / Dresden diaspora locations provided sustained post-2024 demand for the equipment-supplier hub, partially offsetting the post-2022 China-customer-revenue decline.

10. The Semiconductor-Talent-Migration Question and Cross-Strait Talent-Flow Regulations

10.1 The "30,000+ Engineers Exported" Discourse and the Empirical Counter-Evidence

The post-2024 Taiwanese domestic discourse on semiconductor-talent migration to the Arizona, Kumamoto, and Dresden TSMC facilities — articulated through KMT and TPP framings emphasising the "30,000+ engineers exported" frame — operates as a structuring frame for the post-2024 political-coalition contestation on TSMC's global-fab architecture. The empirical counter-evidence: public statements by MOEA Minister Kuo Jyh-huei (郭智輝), TSMC senior management, and the Taiwan Industrial Development Administration have characterised the talent-migration figures as substantially smaller than the 30,000 frame, with the post-2024 Arizona transferred-engineer count in the low thousands. TSMC's investor-call disclosures across 2022–2025 indicated approximately 600–1,000 Taiwan-resident engineers transferred to Arizona per phase of the build-out, with the cumulative through-2024 transferred count approximately 2,000–3,000 [TBD-VERIFY: precise post-2024 TSMC Arizona transferred-Taiwan-engineer cumulative count].

The Kumamoto JASM transfer figures: approximately 320–500 Taiwan-resident engineers transferred through the 2021–2024 build-out cycle [TBD-VERIFY: precise JASM Taiwan-engineer transfer count]. The Dresden ESMC pre-2025 transfer figures: limited transfer activity through the pre-September 2024 ground-breaking period, with the post-2024 build-out cycle expected to transfer approximately 200–400 Taiwan-resident engineers through the pre-2027 ramp [TBD-VERIFY: precise Dresden ESMC Taiwan-engineer transfer projections].

The "30,000+ engineers exported" discourse's analytical genealogy: certain Taiwanese-opposition-framing reporting cited cumulative-over-multi-year figures including indirect-supplier transfers (equipment-supplier engineers, construction-engineer transfers, and the broader semiconductor-supply-chain workforce flow) reaching the 30,000+ frame; the framing's empirical robustness is contested, but its political-discourse efficacy is well-established.

10.2 The Cross-Strait Talent-Flow Regulation Architecture

The cross-Strait talent-flow regulation architecture — operationalised through the post-2023 Trade Secrets Act (營業秘密法) amendments, the post-2024 National Security Act (國家安全法) amendments, and the Ministry of Labour (勞動部), National Security Bureau (國家安全局), and MAC coordination — established the post-2023 legal-regulatory framework for cross-Strait semiconductor-engineer recruitment by PRC-headquartered firms. The post-2023 Trade Secrets Act amendments introduced enhanced criminal penalties for the unauthorised export or transfer of designated "national core key technologies" (國家核心關鍵技術) including specified semiconductor process-technology and design-IP categories. The post-2024 National Security Act amendments designated additional protected technology categories and enhanced the enforcement architecture.

The PRC-side counter-flow architecture — operationalised through SMIC, YMTC, CXMT, and the broader PRC semiconductor industry's recruitment of Taiwanese engineers — produced sustained 2020–2026 cross-Strait talent-competition dynamics. Recruitment vehicles included: direct PRC-firm recruitment with Taiwanese-resident engineers offered relocation packages substantially above Taiwanese-market compensation; Hong Kong-based intermediary firms acting as recruitment-and-administrative-vehicle conduits; Southeast Asian secondment vehicles routing through Vietnamese, Malaysian, and Singaporean intermediary employment arrangements. The post-2024 enforcement track: documented cases of Trade Secrets Act prosecutions of Taiwanese-resident engineers for unauthorised technology transfer; the post-2024 National Security Act enforcement actions; the post-2024 Bureau of Foreign Trade enhanced end-user-verification requirements.

10.3 The Domestic-Talent-Pipeline Architecture

The post-2020 domestic-talent-pipeline architecture — operationalised through the Ministry of Education (教育部) post-2020 Strategic Industry Talent Cultivation framework, the National Tsing Hua University, National Yang Ming Chiao Tung University, National Cheng Kung University, and National Taiwan University semiconductor-research-track expansion — addresses the post-2020 domestic-talent-pipeline constraints. The post-2021 Act for the Establishment of National Yang Ming Chiao Tung University Semiconductor Research Institute (國立陽明交通大學產學創新研究學院設置條例) and the post-2021 corresponding acts at NTHU, NCKU, and NTU established the dedicated semiconductor-research-track expansion. The post-2020 international-talent-recruitment framework — operationalised through the post-2017 Act for the Recruitment and Employment of Foreign Professionals (外國專業人才延攬及僱用法) and the post-2023 revisions — established the post-2024 international-engineer recruitment architecture, with the post-2024 emphasis on Vietnamese, Indian, and Indonesian engineering-graduate recruitment to address the post-2024 domestic-talent constraints.

11. The Lai Government Chip-Diplomacy Doctrine and the MOEA Architecture (2024–2026)

11.1 The Post-May 2024 Lai-Administration Chip-Diplomacy Architecture

The post-May 2024 Lai-administration chip-diplomacy architecture — operationalised under MOEA Minister Kuo Jyh-huei (郭智輝, sworn in 20 May 2024) and Vice Minister Chen Cheng-chi (陳正祺) — constitutes the post-2024 strategic-coordination architecture for TSMC's global-fab trajectory, Taiwan's domestic-investment retention, and the post-2024 US-Japan-EU semiconductor-supply-chain coordination. Kuo Jyh-huei — pre-2024 founding chairman of Topco Scientific (崇越科技), the principal Taiwan-headquartered semiconductor-supply-chain logistics firm — brought to the MOEA Minister position substantial private-sector semiconductor-industry experience and operationalised the post-2024 chip-diplomacy doctrine through sustained engagement with TSMC, the US Department of Commerce, METI, and DG CONNECT.

The Lai-administration silicon-shield-2.0 framing — articulated through Lai's 20 May 2024 inaugural address, the post-March 2025 Seventeen Tasks (十七項任務) framework, the post-September 2024 Dresden ESMC ground-breaking attendance, and the May 2025 first-anniversary speech — characterises TSMC's global-fab architecture as deepening rather than diluting cross-Strait deterrence weight. The framing's principal contention: by embedding Taiwan-controlled production capacity in the strategic-supply-chain architecture of the United States, Japan, and the European Union, the post-2020 trajectory produces reciprocal-political-investment in Taiwan's strategic position that complements the pre-2020 single-geography concentration-based deterrence weight. The framing's contested reception: KMT and TPP critiques (anchored at TW-D-04 and TW-D-06) characterise the post-2024 trajectory as risking long-term industrial-base erosion; structural-political-economy framings (CSIS, Brookings, Atlantic Council) characterise the post-2024 trajectory as the operationalisation of US-China strategic decoupling in the semiconductor sector with Taiwan operating as the principal pivot variable.

11.2 The Post-March 2025 Seventeen Tasks Framework

The post-March 2025 Seventeen Tasks (十七項任務) framework — announced in the post-3 March 2025 Oval-Office-announcement domestic-response cycle [TBD-VERIFY: precise Seventeen Tasks framework announcement date in March 2025] — operationalises the post-2024 Lai-administration coordinated response to the Trump-2 negotiating-track architecture. The framework's seventeen tasks cover: (1) the Taiwan-US trade-negotiating-track activity coordinated through the Office of Trade Negotiations (OTN) under Vice Premier Cheng Li-chiun (鄭麗君); (2) the Taiwan-side procurement-offer framework covering liquefied natural gas, agricultural, and defence-related procurement; (3) the post-March 2025 strategic-supply-chain coordination with the US Department of Commerce; (4) the post-2025 Taiwan Industrial Innovation Act revision; (5) the post-2025 Kaohsiung Science Park anchor for N2 and below domestic production; (6) the post-2024 talent-retention framework expansion; (7) the post-2024 cross-Strait talent-flow regulation enforcement; (8–17) additional tasks covering economic-resilience, military-resilience, energy-resilience, agricultural-resilience, and cyber-resilience axes [TBD-VERIFY: precise composition of the post-March 2025 Seventeen Tasks framework].

11.3 The Post-2024 Coordinated International-Engagement Track

The post-2024 coordinated international-engagement track — operationalised through the OTN under Cheng Li-chiun, the MOEA International Trade Administration under Roy Lee (李淳), and the Office of the President's National Security Council under Secretary-General Joseph Wu (吳釗燮) — sustains the post-2024 strategic-coordination with the US Department of Commerce (under Secretary Howard Lutnick from January 2025), Japanese METI (under successive METI Ministers including Saito Ken (斎藤健) and post-2024 Muto Yoji (武藤容治)), German BMWK (under Federal Minister Robert Habeck, post-November 2024 transition), and EU DG CONNECT. The post-2024 engagement-track principal milestones: the post-September 2024 Dresden ESMC ground-breaking; the post-March 2025 Oval-Office Wei-Trump announcement; the post-April 2025 USTR negotiating-track activity; the post-2025 Taiwan-Japan strategic-supply-chain coordination meeting cycle; the post-2026 second-anniversary assessment cycle.

12. Three-Account Discipline — Silicon-Shield Insurance vs Supply-Chain Weakening; CHIPS Act Industrial Policy vs Trade-Policy Theatre; Export Controls Containing or Accelerating Chinese Indigenisation

12.1 First Account — "Is TSMC's Global Expansion Silicon-Shield Insurance or Supply-Chain Weakening?"

The first three-account-discipline question — whether TSMC's post-2020 global expansion operates as silicon-shield insurance (deterrence-thickening) or supply-chain weakening (deterrence-dilution) — partitions across the Lai-administration, KMT-Han, and industry-analyst readings.

The Lai-administration silicon-shield-2.0 affirmative reading: the post-2020 geographic-diversification embeds Taiwan-controlled production capacity in the strategic-supply-chain architecture of the United States, Japan, and the European Union, producing reciprocal-political-investment in Taiwan's strategic position that exceeds the pre-2020 single-geography concentration-based deterrence weight. The argumentative architecture: the post-2024 US, Japanese, and European governmental-and-private-sector strategic-economic stake in TSMC's continuing operations creates an additional political-economic dimension to cross-Strait deterrence that operates in parallel to the pre-2020 cost-imposition logic. The post-March 2025 Oval-Office pledge, the post-February 2024 JASM Fab 1 opening, and the post-September 2024 Dresden ESMC ground-breaking are characterised as deterrence-thickening rather than dilution.

The KMT-Han-critical reading — articulated by Han Kuo-yu (韓國瑜, Legislative Yuan Speaker), KMT Chair Eric Chu (朱立倫), and 2024 KMT vice-presidential candidate Jaw Shaw-kong (趙少康) — emphasises the costs of forced capital-and-talent migration from Taiwan to the United States. The argumentative architecture: the post-2020 trajectory transfers Taiwanese strategic-industrial capacity to overseas locations under post-2024 political-economic pressure; the post-3 March 2025 Oval-Office pledge represents concession under pressure rather than strategic positioning; the long-term-erosion concern is that the post-2020 trajectory may dilute rather than thicken the silicon-shield deterrence weight by producing the substitution-capacity (Arizona, Kumamoto, Dresden) that would partially insulate the global semiconductor architecture from Taiwan-located disruption.

The industry-analyst reading — articulated by CSIS Bonny Lin, Brookings Ryan Hass, Atlantic Council Sung Wen-Ti, and the broader industry-analyst commentary — emphasises the empirical-question dimension: whether the post-2020 geographic-diversification produces meaningful substitution capacity for Taiwan-located production within the post-2030 strategic-window. The technical-analytical sub-question: the Arizona Phase 1 N4, the Phase 2 N3, and the Phase 3 N2 architecture together produce approximately 20–25 per cent of TSMC's post-2030 advanced-process capacity, with the Taiwan-located Hsinchu / Tainan / Kaohsiung concentration retaining approximately 75–80 per cent of TSMC's post-2030 advanced-process capacity. The deterrence-or-dilution interpretation depends on whether the post-2030 Taiwan-concentration retention is sufficient to maintain the pre-2020 silicon-shield deterrence-weight or whether the post-2030 geographic-diversification produces sufficient substitution-capacity to alter the strategic-calculation framework.

12.2 Second Account — "Is the CHIPS Act Real Industrial Policy or Trade-Policy Theatre?"

The second three-account-discipline question — whether the August 2022 CHIPS and Science Act operates as substantive industrial policy or as trade-policy theatre — partitions across US-government, ITIF-pro-industrial, and Cato-critical-libertarian readings.

The US-government affirmative reading: the CHIPS Act's USD 39 billion direct-subsidy authorisation, the 25 per cent investment tax credit, and the USD 13.2 billion R&D / workforce / Manufacturing USA authorisation constitute the most-substantial US industrial-policy intervention in the semiconductor sector since the 1980s SEMATECH initiative. The empirical evidence: the post-2022 announcement of approximately USD 400 billion in cumulative US semiconductor-manufacturing capital-expenditure commitment across TSMC, Intel, Samsung, Micron, GlobalFoundries, and the broader supplier base; the post-2024 commencement of commercial-volume production at TSMC Arizona Fab-21 Phase 1; the post-2024 progression at Intel Ohio, Samsung Taylor, and Micron New York / Idaho. The reading's principal contention: the CHIPS Act is producing measurable industrial-policy outcomes within the planned 2022–2030 implementation window.

The ITIF (Information Technology and Innovation Foundation, under President Robert D. Atkinson) pro-industrial reading: the CHIPS Act represents the post-1980s US recognition that the laissez-faire industrial-policy framework had produced structural-industrial-base erosion in critical technology sectors, and that coordinated industrial-policy intervention is both warranted and effective. The argumentative architecture: the post-2022 CHIPS Act is one component of the broader post-2020 US industrial-policy renaissance including the Inflation Reduction Act (IRA, August 2022), the Infrastructure Investment and Jobs Act (IIJA, November 2021), and the post-2022 strategic-supply-chain coordination architecture. The ITIF reading characterises the post-2022 industrial-policy trajectory as the structural-reorientation of US economic strategy away from the post-1980s laissez-faire framework.

The Cato-critical-libertarian reading — articulated by Cato Institute scholars including Scott Lincicome and Adam Posen — characterises the CHIPS Act as ineffective or counter-productive industrial policy that imposes substantial public expenditure on private-sector activities that would have occurred without subsidy. The argumentative architecture: the post-2022 TSMC, Intel, Samsung, and Micron US-located investment was driven principally by customer geographic-diversification demand, cross-Strait risk profile considerations, and strategic-supply-chain coordination — not by the CHIPS Act subsidy. The reading's empirical contention: removing the CHIPS Act subsidy would have produced substantially similar post-2022 US-located capital-expenditure outcomes at substantially lower public cost. The post-Trump-2 redirection threat is characterised as the appropriate political-economic correction of the post-2022 Biden-era industrial-policy overreach.

12.3 Third Account — "Is the Export-Control Regime Containing or Accelerating Chinese Indigenisation?"

The third three-account-discipline question — whether the post-October 2022 BIS export-control regime is containing or accelerating Chinese semiconductor indigenisation — partitions across BIS-hawks, SMIC-progression-empirical, and Carnegie-Mark-Hannah readings.

The BIS-hawks reading — articulated by Gregory Allen (CSIS), Sujai Shivakumar (CSIS), and the post-2022 BIS leadership — characterises the post-2022 export-control regime as effectively containing Chinese semiconductor indigenisation within the strategic-window relevant to US-China competition. The argumentative architecture: the post-2022 BIS restrictions have prevented Chinese access to leading-edge EUV lithography (the principal strategic-bottleneck for sub-7-nanometre process indigenisation); the post-2022 cumulative-effect produces a 5-to-10-year delay in Chinese leading-edge process indigenisation that is strategically meaningful within the post-2025 strategic-competition window. The August 2023 Huawei Mate 60 Pro / Kirin 9000S launch is characterised as expected but not strategic-threat-level given the 7-nanometre process's yield, cost, and volume profile constraints relative to TSMC-produced equivalent products.

The SMIC-progression-empirical reading — articulated by TechInsights, IC Insights, certain industry-analyst commentary, and the post-2023 PRC-side analytical framings — characterises the post-2022 SMIC 7-nanometre commercial-volume production as evidence that the post-2022 BIS export-control regime has not fully prevented PRC advanced-process progression. The argumentative architecture: SMIC's post-2022 development of 7-nanometre production through DUV multi-patterning techniques demonstrates that the BIS export-control regime's principal strategic-bottleneck (EUV lithography restriction) can be partially circumvented through alternative process-engineering pathways; the post-2024 Huawei Ascend 910B / 910C trajectory provides additional evidence of commercial-volume AI-accelerator production at the 7-nanometre node within the PRC industrial base.

The Carnegie-Mark-Hannah reading — articulated by Mark Hannah (Eurasia Group Foundation), certain Carnegie Endowment scholars, and academic-economist analyses — characterises the post-2022 BIS export-control regime as counter-productive in accelerating Chinese strategic prioritisation of semiconductor self-sufficiency. The argumentative architecture: the post-2022 BIS restrictions have produced the principal motivating event for the post-2024 Big Fund Phase 3 (RMB 344 billion) and the broader post-2024 PRC "new productive forces" framework concentrating on semiconductor indigenisation; the post-2022 trajectory has produced the structural-political-economic incentive for the PRC industrial base to develop substitution capacity that may, over the post-2030 horizon, exceed the pre-2022 PRC semiconductor-industrial-base trajectory. The reading's strategic-implication: the post-2022 BIS regime may have produced short-term containment effects but at the cost of long-term acceleration of Chinese semiconductor indigenisation.

13. Conclusion and Forward View — The Post-2026 Trajectory and the Silicon-Shield 2.0 Architecture

13.1 The Post-2026 Operational State

As of May 2026 — two years into the Lai administration's first term — the post-2020 semiconductor-diaspora architecture is in operational maturation across the three principal sites: Arizona Fab-21 Phase 1 N4 production has reached yield parity with the Tainan Fab 18 baseline through Q1 2025 and is operating at commercial volume through 2025–2026; Kumamoto JASM Fab 1 is in stable 12–28nm production with Fab 2 in advanced construction targeting 2027 mass production at 6–7nm; Dresden ESMC ground-work is progressing toward the 2027/2028 production-start target with the post-September 2024 ground-breaking architecture operationalising; and the post-March 2025 Trump-Wei Oval-Office Phase 3 N2 trajectory is in early-construction phase with the 2030 production-start target.

The post-2026 cumulative-capacity profile: TSMC's post-2030 leading-edge (N2 and below) capacity is projected at approximately 75–80 per cent Taiwan-located (across the Hsinchu Fab 20, Tainan Fab 18, and Kaohsiung Fab 22 anchors) and approximately 20–25 per cent Arizona-located (across the Phase 1, Phase 2, and Phase 3 architecture). The post-2030 mid-node (N6 / N7 / N12 / N16 / N22 / N28) capacity is projected at approximately 65–70 per cent Taiwan-located, approximately 15–20 per cent Kumamoto-located (across JASM Fab 1 and Fab 2), and approximately 10–15 per cent Dresden-located (the post-2027 ESMC production architecture). The capacity-distribution profile reflects the post-2024 dual-track architecture: leading-edge concentration retained in Taiwan with substantial Arizona diversification; mid-node geographic-diversification across Japan and Europe with sustained Taiwanese-domestic anchor.

13.2 The Post-2026 Forward-Trajectory Variables

The post-2026 forward-trajectory variables: (a) the post-Section-232 tariff outcome and the post-April 2025 reciprocal-tariff negotiating-track resolution; (b) the post-2026 Taiwan local-elections political-coalition signal and the post-2028 presidential-election trajectory; (c) the post-2027 Dresden ESMC and Kumamoto JASM Fab 2 production-start operationalisation; (d) the post-2028 Arizona Phase 2 N3 production-start; (e) the post-2030 Arizona Phase 3 N2 production-start; (f) the post-2026 PRC semiconductor-indigenisation progression including the SMIC 5-nanometre development trajectory and the post-2024 Big Fund Phase 3 deployment cycle; (g) the post-2026 cross-Strait deterrence-and-coercion architecture including the post-Lai-second-term PRC pressure trajectory.

13.3 The Silicon-Shield 2.0 Architecture — Interpretive Synthesis

The silicon-shield 2.0 interpretive synthesis: the post-2020 trajectory has structurally reorganised the silicon-shield doctrine from a single-geography concentration-based framework (the pre-2020 Hsinchu / Tainan / Taichung concentration as the principal cost-imposition logic) to a multi-geography distributed framework (the post-2020 Taiwan / Arizona / Kumamoto / Dresden architecture as the broader strategic-supply-chain coupling logic). The reorganisation's deterrence-or-dilution interpretation remains contested across DPP / KMT / TPP political-coalition framings and across CSIS / Brookings / ITIF / Cato / Carnegie analytical framings. The integrative reading: the post-2020 silicon-shield 2.0 architecture operates simultaneously as cross-Strait deterrence-thickening (through US-Japan-EU strategic-supply-chain coupling) and as long-term Taiwanese industrial-base-erosion risk (through forced capital-and-talent migration). The forward-trajectory window: the post-2026 to post-2030 strategic-window is the principal operational test of the silicon-shield 2.0 architecture's deterrence-or-dilution profile, with the post-2026 PRC pressure trajectory (anchored at TW-F-04 and the broader cross-Strait military balance), the post-2027 Dresden / Kumamoto production-start, and the post-2030 Arizona Phase 3 N2 production-start operating as the principal post-2026 inflection points.

The spiral index of related documents and the broader corpus connections: this document operates as the Block-G Level-1 Anchor for the post-2020 Taiwan semiconductor-diaspora trajectory, with sustained connections to: TW-D-02 (the Lai Ching-te presidency, providing the political-coalition-and-governance context for the post-2024 chip-diplomacy doctrine); TW-D-03 (the Arizona-specific industrial-policy-and-tariff window, with which TW-G-03 shares the post-March 2025 Oval-Office-pledge and post-April 2025 tariff-architecture material); TW-D-04 (the 2025 KMT recall campaign, providing the political-coalition-contestation context); TW-D-05 (the Lai mid-term and 2026 local elections, providing the electoral-signal context); TW-D-06 (the Taiwan 2026 budget battle and the post-2025 defence-spending and industrial-policy fiscal architecture); TW-F-04 (the cross-Strait military balance, providing the deterrence-architecture context within which the silicon-shield 2.0 framing operates); TW-G-01 (the foundational TSMC and semiconductor-industry history); TW-G-02 (the broader Taiwan semiconductor ecosystem beyond TSMC); JP-F-05 (the Japan-Taiwan strategic alignment, providing the Kumamoto JASM coordination context); US-F-07 (the US-China strategic decoupling architecture, providing the broader export-control and industrial-policy context); US-D-10 (the Trump-2 tariff architecture, providing the post-January 2025 US trade-policy context); CN-F-01 (the China-Russia partnership and the broader geopolitical context); CN-D-04 (the China 2026 Two Sessions and the "new productive forces" framework, providing the PRC industrial-policy context). The post-2026 forward-research agenda concentrates on the post-Section-232 outcome, the post-2027 Dresden / Kumamoto production-start, the post-2028 Arizona Phase 2 N3 production-start, and the post-2026 cross-Strait political-economic trajectory.

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Japan Advanced Semiconductor Manufacturing (JASM, 日本先端半導體製造株式會社), public disclosures and the Sony Semiconductor Solutions / DENSO Corporation / Toyota Motor Corporation joint-venture documentation 2021–2026. JASM Fab 1 opened in February 2024 in Kikuyo, Kumamoto Prefecture, producing 12-nanometre, 16-nanometre, 22-nanometre, and 28-nanometre logic chips with image-sensor packaging integration; JASM Fab 2 ground-breaking in late 2024 / early 2025 targeting 6-nanometre and 7-nanometre production by 2027.
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ASML Holding NV, quarterly earnings-call transcripts 2020–2026, with particular reference to the EUV (extreme ultraviolet) and DUV (deep ultraviolet) lithography-equipment shipment patterns to Taiwan, the United States, South Korea, Japan, and China; the post-2023 BIS-imposed export-licence restrictions affecting Chinese customers; the post-September 2023 Dutch government export-control coordination; and the TSMC global-fab EUV install-base timeline disclosures.
Applied Materials, Inc., KLA Corporation, Lam Research Corporation, Tokyo Electron Ltd., and Hitachi High-Tech Corporation — quarterly earnings-call transcripts and SEC / Tokyo Stock Exchange filings 2020–2026 referencing the post-October 2022 BIS rule impacts on China-customer revenues and the parallel TSMC Arizona / Kumamoto / Dresden supply-chain ramp.
United Microelectronics Corporation (UMC, 聯華電子股份有限公司), Vanguard International Semiconductor (VIS, 世界先進), Powerchip Semiconductor Manufacturing Corporation (PSMC, 力積電), Macronix International Co., Ltd. (旺宏電子), Nanya Technology Corporation (南亞科技), and Inotera Memories, Inc. (華亞科技, now part of Micron Memory Taiwan) — annual reports, quarterly earnings calls, and Taiwan Stock Exchange (TWSE) filings 2020–2026.
GlobalWafers Co., Ltd. (環球晶圓), annual reports and TWSE filings 2020–2026, with reference to the post-2022 silicon-wafer supply-chain geographic-diversification trajectory including the Sherman, Texas (US), GlobalWafers America facility ground-breaking in late 2022 and the post-2024 production-ramp.
PSMC-Tata Electronics Dholera joint-venture documentation 2024–2026, including the February 2024 Tata Group announcement of the Dholera (Gujarat) semiconductor fab in collaboration with PSMC providing process-technology licensing, with the post-2024 ground-breaking and the post-2026 production-start trajectory [TBD-VERIFY: the exact PSMC-Tata equity-and-licensing architecture has varied across reporting cycles; the licensing-rather-than-equity framing is the operative public characterisation].
Semiconductor Manufacturing International Corporation (SMIC, 中芯國際), Yangtze Memory Technologies Corporation (YMTC, 长江存储), Changxin Memory Technologies (CXMT, 长鑫存储), Huawei Technologies Co., Ltd. (华为), and the broader PRC semiconductor-industry public disclosures 2020–2026, with reference to: SMIC's post-2022 7-nanometre process indigenisation progression; the August 2023 Huawei Mate 60 Pro launch with the Kirin 9000S processor and the indication of SMIC 7-nanometre commercial production capability; the post-2024 Huawei Ascend 910B / 910C AI-accelerator-chip production trajectory.
Center for Strategic and International Studies (CSIS), Washington DC: Bonny Lin, Trustee Chair in Taiwan Studies, post-2023 sustained commentary; Bonnie S. Glaser (German Marshall Fund Indo-Pacific Director); Sujai Shivakumar, Renewing American Innovation Project director; Gregory C. Allen (CSIS Wadhwani Center for AI and Advanced Technologies), export-controls and Section 232 analyses 2022–2026.
Information Technology and Innovation Foundation (ITIF), Washington DC: Robert D. Atkinson, President, sustained pro-industrial-policy commentary 2020–2026; the post-2022 CHIPS Act analyses; the 2024–2025 ITIF semiconductor-industrial-policy programme materials.
Brookings Institution semiconductor work 2020–2026: Patricia Schouker; John VerWey; Ryan Hass (East Asia foreign-policy adjacent commentary).
Council on Foreign Relations (CFR) The Battle for Semiconductor Supremacy brief series 2022–2026; Hudson Institute Taiwan papers 2022–2026.
SEMI (Semiconductor Equipment and Materials International) industry reports, Gartner industry analyses, IC Insights / TechInsights industry analyses, and TrendForce industry analyses 2020–2026.
Nikkei Asia semiconductor coverage (Cheng Ting-fang; Lauly Li; Yifan Yu); Bloomberg semiconductor coverage (Yang Jie; Debby Wu; Mayumi Negishi); Reuters Taipei bureau (Yimou Lee; Sarah Wu); Financial Times (Kathrin Hille; Eleanor Olcott); Wall Street Journal (Yang Jie; Jiyoung Sohn); DIGITIMES Taiwan; Commonwealth Magazine (《天下雜誌》) industrial-policy coverage — sustained 2020–2026 archival coverage.
Chris Miller, Chip War: The Fight for the World's Most Critical Technology (Scribner, October 2022), the foundational synthetic history of the global-semiconductor architecture; sustained 2022–2026 Foreign Policy, Financial Times, and Tufts Fletcher School commentary.
Mainland Affairs Council of the Republic of China (MAC, 大陸委員會), cross-Strait economic-and-trade-flow statistical reports 2020–2026, including post-2024 quarterly reports tracking the post-October 2022 / October 2023 / December 2024 export-control regime's effects on Taiwan-China semiconductor-supply-chain flows; the Investment Commission (投資審議司, post-September 2023 reorganisation of the former Investment Commission) outbound-investment screening data 2020–2026.

TW-D-02: The Lai Ching-te Presidency (2024–2025) — sibling Block-D Level-1 Anchor; TW-D-02 concentrates the legislative-reform-and-cross-Strait-deterrence threading; TW-G-03 concentrates the semiconductor-diaspora and chip-diplomacy threading.
TW-D-03: TSMC Arizona, the CHIPS and Science Act, and the Trump-2 Chip-Tariff Regime (2020–2025) — direct anchor companion; TW-D-03 concentrates the Arizona-specific industrial-policy-and-tariff window; TW-G-03 treats the full TSMC global-fab architecture (Arizona, Kumamoto, Dresden) and the broader semiconductor-diaspora.
TW-D-04: The 2025 KMT Recall Campaign — political-coalition context for the post-2024 chip-diplomacy contestation.
TW-D-05: Lai Mid-Term — 2026 Local Elections and Recall Aftermath — political-trajectory companion for the chip-diplomacy-related polling and electoral signals.
TW-D-06: Taiwan 2026 Budget Battle — KMT-TPP Bloc Confrontation and Defence Spending — budget-coalition context for the post-2025 Taiwan Industrial Innovation Act revision.
TW-F-04: Cross-Strait Military Balance, Asymmetric Defence, and the Overall Defense Concept (2017–2026) — military-balance anchor; the silicon-shield doctrine's military-deterrence dimension operates in interaction with the asymmetric-defence trajectory.
TW-G-01: TSMC and the Semiconductor Industry — thematic-economic anchor; TW-G-01 treats the founding-to-present TSMC institutional history; TW-G-03 concentrates the 2020–2026 global-diversification window.
TW-G-02: Taiwan's Semiconductor Ecosystem Beyond TSMC (1987–2025) — ecosystem-architecture anchor; TW-G-02 treats UMC, MediaTek, Realtek, ASE, and the broader ecosystem; TW-G-03 concentrates the 2020–2026 diaspora trajectory.
JP-F-05: Japan-Taiwan Strategic Alignment (2022–2026) — bilateral-companion document; the Kumamoto JASM project operates within the broader Japan-Taiwan strategic-alignment trajectory.
US-F-07: US-China Strategic Decoupling, Export Controls, and Investment Screening (2022–2026) — US-side anchor; the BIS export-control regime and the CHIPS Act conditionality operate within the broader decoupling architecture.
US-D-10: Trump-2 Tariff Architecture — US-side political-economy anchor; the post-2 April 2025 reciprocal-tariff regime operates within the broader Trump-2 tariff architecture.
CN-F-01: China-Russia Partnership — broader-geopolitical context; the PRC semiconductor-indigenisation trajectory operates within the broader China-Russia / Eurasian-bloc geopolitical architecture.
CN-D-04: China 2026 Two Sessions — New Productive Forces — PRC-side political-economy anchor; the post-2024 PRC semiconductor-industrial-policy direction operates within the broader "new productive forces" (新质生产力) framework.
TW-H-PRES-04: Tsai Ing-wen — 蔡英文
TW-D-01: The 13 January 2024 Taiwan Presidential Election, the Lai-Hou-Ko Three-Way Race, and the DPP's Three Consecutive Presidencies — the First Since Taiwan's Democratisation
TW-K-01: Tsai Ing-wen's 2 January 2019 "Five Musts" Rejection of Xi Jinping's Message to Compatriots in Taiwan 40th-Anniversary Address — the Same-Day Office of the President Response, the Domestic-Political Inflection Point that Restored the 2020 Re-Election Campaign, and the Cross-Strait Consequences
TW-G-04: The Hsinchu Science Park and the Taiwan Semiconductor Industrial-Policy Architecture — From the 15 December 1980 Founding under Premier Sun Yun-suan to the Post-2025 Trump-2 Export-Control and Capacity-Diversification Era
TW-K-02: The Tsai Administration's 2017 Pension Reform Decision and the Post-Reform Political Cost — The 27 June 2017 Civil Service Pension Act and the 29 June 2017 Teachers' Pension Act Reducing the 18 Per Cent Preferential Interest Rate, the 23 April 2017 KMT-Aligned Veterans-and-Pensioners Protest at the Legislative Yuan, and the Short-Term Approval Crash to Approximately 30 Per Cent Against the Structural Fiscal Stability Gain
TW-F-02: Cross-Strait Dynamics 2000–2026 — From Chen Shui-bian's Independence Rhetoric to Lai Ching-te's Deterrence-Dependence Equilibrium
TW-C-09: The Lai Ching-te Presidency Year Two — Divided-Government Stability, the Post-Great Recall Aftermath, the FY2026 Budget Battle and 3-Per-Cent-of-GDP Defence-Spending Question, the Hsiao Bi-khim Vice-Presidential Role, and the Trump-2 US-Taiwan Trade-Negotiating-Track Continuation
TW-E-01: The Economic Cooperation Framework Agreement and the Twenty-Three Cross-Strait Agreements — From the 12 June 2008 Beijing ARATS-SEF Resumption and the 29 June 2010 Chongqing ECFA Signing to the 2014 Sunflower CSSTA Suspension, the Post-2016 DPP Partial Maintenance, and the Post-2024 Lai-Era PRC Suspension Threats
TW-E-02: Taiwan's New Southbound Policy — From the 20 May 2016 Tsai Inaugural Strategic-Reorientation Announcement and the 5 September 2016 Executive Yuan Policy-Guideline Release to the Eighteen-Target-Country Architecture across the Ten ASEAN Members, the Six South Asian States, and the Australia–New Zealand Pair, the Post-2020 CPTPP Application Trajectory, and the Post-20 May 2024 Lai-Era Continuation
TW-K-03: The 7 November 2015 Ma Ying-jeou – Xi Jinping Singapore Meeting Decision — the First Face-to-Face Encounter Between Heads of State of the Republic of China and the People's Republic of China since the 1945 Chongqing Chiang–Mao Meeting, the October–November 2015 Decision Sequence, the Shangri-La Hotel 79-Minute Closed Session and the "Mr Ma" / "Mr Xi" Form-of-Address Mechanism, the Symbolic-versus-Substantive Contestation, and the Post-2016 DPP-Era Reassessment
TW-N-01: Taiwan in International Perceptions — Chip Island, Beacon, and Flashpoint
TW-G-05: Taiwan Energy Policy, Nuclear Politics, and the Security-of-Supply Question — From the 1978 Chinshan Reactor Start-Up through the Nuclear-Free-Homeland Phase-Out to the Post-2024 Reversal Debate
TW-O-01: Taiwan Megatrends — The 2030s Questions
TW-F-03: The New Southbound Policy and Taiwan's Southeast Asia Turn